Synthesis of Digital Logical System by Using Logical Function Decomposition Algorithms implemented with PLD - Programmable Logic Devices

The decomposition problem is old, and well understood when the function to be decomposed is specified by a truth table or has one output only. The paper consists of the use of some logical function decomposition algorithms with application in the implementation of classical circuits like SSI, MSI and PLD. The decomposition methods use the Boolean matrix calculation. It is calculated the implementation costs emphasizing the most economical solutions. We have considered a circuit PAL10L8, which has 10 inputs, 8 outputs and an AND-OR configuration, each NOR having 2 inputs. One important aspect of serial decomposition is the task of selecting ’best candidate’ variables for the G function. Decomposition is essentially a process of substituting two or more input variables with a lesser number of new variables. This substitution results in the reduction of the number of rows in the truth table. Hence, we look for variables which are most likely to reduce the number of rows in the truth table as a result of decomposition. Let us consider an input variable purposely avoiding all inter-relationships among the input variables. The only available parameter to evaluate its "activity" is the number of ’l’s or ’O’s it has in the truth table. If the variable has only ’1’ s or ’0’ s it is the "best candidate" for decomposition, as it is practically redundant. The paper showed that the use of the Boolean function decomposition method reduces the number of circuits necessary for the implementation.