A Fast-Lock Low-Jitter DLL with Double Edge Synchronization in 0.18µm CMOS Technology

Aims: This paper describes a fast-lock, low-power, low-jitter and good duty-cycle correction capability delay locked loop with double edge synchronization which is mainly used in clock alignment process. A clock aligner’s task is to phase-align a chip internal clock with a reference clock. The main advantage of delay locked loop rather than phase locked loop is related to good jitter performance of it. Double edge synchronization method leads to more power consumption and it can increase rms and peak-to-peak jitter therefore, in this work rms jitter, peak-to-peak jitter and power consumption are implemented to understand if this statement is always true or not. So, this case became one of our aims.
Study Design: Double edge synchronization delay locked loop.
Place and Duration of Study: Department of Electrical Engineering (Islamic Azad University, Central Tehran Branch), between February 2012 and September 2012.
Methodology: Comparing with single edge synchronization delay locked loops, double edge synchronization method has its own advantages and disadvantages. Using two phase frequency detectors, two charge pumps and two loop filters in double edge delay locked loops, increases the jitter and power consumption. In this paper, to overcome these challenges for the introduced delay locked loop circuit, proper blocks with suitable characteristic for each MOSFET were used which took a lot of time to find ones with the help of HSPICE simulator.
Results: All the simulation results are based on 0.18μm CMOS technology with 1.8V supply voltage. The HSPICE simulation results show the proposed delay locked loop circuit generates clock signals ranging from 750MHz to 1GHz. The maximum power consumption of the DLL circuit at 1GHz is 3.4mW. The maximum and minimum of rms jitters are 9.12 and 0.463ps and the maximum and minimum of peak-to-peak jitters are 124.89 and 2.52ps, respectively. The locking time of proposed delay locked loop is less than 20ns within the operating frequency band. Another feature of this architecture is that it has good duty cycle correction capability (50±0.9%). It should be note that, in double edge DLL it is so important to find a balance between duty cycle (should be around 50%), jitter and power consumption. Rms jitter, peak-to-peak jitter, power consumption and also duty cycle error are calculated by HSPICE simulator. (Cosmosscope program in HSPICE simulator can be used for these measurements).
Conclusion: Although designing double edge synchronization method in delay locked loops is challenging and it takes more area than single edge delay locked loops (which is mentioned as the main disadvantages of double edge delay locked loops and we all agree on this), by choosing suitable blocks it can be used without jitter performance or power consumption challenges. In other word, the results of this paper shows that all the effective and important items of introduced double edge delay locked loop (such as power consumption, rms jitter and peak-to-peak jitter) are as well as single edge delay locked loops in most articles. So when it is suitable to use double edge delay locked loop instead of single edge delay locked loop, it should be no concern about these items.